RISC-V or RISC in general not really they are simply the low level CPU model done in a particular way. SIMD I think classifies the same way its still doing low level operations like Adds, Mpys etc but it reduces the overhead if issuing them in larger batches say 32 at a time.
I mean some cpu instructions match high level operations done on lists. Loading of arrays of structs, efficient operations on arrays, it feels like the discussions just ignore all this.
