This also leaves more power & thermal allowance for the IO Hub on the CPU chip and I guess the CPU is cheaper too.
If your workload is mostly about DMAing large chunks of data around between devices and you still want to examine the chunk/packet headers (but not touch all payload) on the CPU, this could be a good choice. You should have the full PCIe/DRAM bandwidth if all CCDs are active.
Edit: Worth noting that a DMA between PCIe and RAM still goes through the IO Hub (Uncore on Intel) inside the CPU.
Then I'm surprised. It's much different to the usual situation when even mass made products are either banned or very limited, e.g. unicycles prohibited, e-scooters only up to 20 km/h, e-bikes only up to 25 km/h.
in the end, it all comes down to roi; if spending x dollars a month brings in an additional 5x revenue then its gonna be worth?
then again, i have some suspicion that alot of consumer-focused end products using llms in the backend (hello chatbots) expecting big returns for all those tokens spent may have some bad news coming... if the bubble starts popping i'm guessing it starts there...
Never thought the difference mastering writing can be so significant. Just like to add what I understand regarding this. It's rather about not making any mistake writing by hand ca. 1-2 DIN A4 pages while someone reads a text (slow enough). I can't remember exactly but making only one (or two) mistake(s) and it is not anymore excellent (just good). Making 4-7 mistakes and it is not good (just sufficient). Making few more and it is bad which means failed. It's a long text with a very short path to fail.
Ukrainian is less difficult to write. There are claims that standardization/reform of Russian made it more artificial (far from natural people language) with overtaking too many words from Latin languages. When I read / listen to Belorussian I think they have even more luck with matching pronunciation/writing than Ukrainian. Which suggests this language is even closer to the common roots old language. (I'm not a linguist.)
Poles will hate me saying this, but I've always really struggled with their orthography, even though I am used to the Roman alphabet. I can see what is going on in Belarusian, Russian and Ukrainian, maybe even Czech to some extent. Polish is bizarre. Szcz is one letter in Cyrillic. I'm still baffled by l with the line through it.
Is there any as large as possible single source (or normal with amalgamation version) more or less meaningful project that could be compiled directly with rustc -o executable src.rs? Just to compare build time / memory consumption.
Yes, that's why I've asked about possible rust support of creating such version of normal project. The main issue, I'm unaware of comparably large rust projects without 3rdparty dependencies.
I believe ripgrep has only or mostly dependencies that the main author also controls. It's structured so that ripgrep depends on regex crates by the same author, for example.
The tradeoff on one program can influence the other program needing perhaps the opposite decision of such tradeoff. Thus we need the arbiter in the kernel to be able to control what is more important for the whole system. So my guess.
> This increases the maximum core count per chiplet from 8 to 12. Furthermore, it increases the L3 cache per CCX/CCD from 32 MB to 48 MB.
I'd say the amount of L3 is not increased but adapted/scaled to the increased core count, since per each core there is still the same amount of cache available as before.
We get faster cores, so we need to get from 5600 to e.g. 6000 DDR5. Since core count is increased by 50%, we'd need 9000... DDR5^W, well yes, we'd need actually as planed before AM6 and DDR6!
There are already DDR5 CUDIMMs at and above 8000 MT/s, and 9600 MT/s has been demonstrated but none are currently in stock. By the time AMD ships Zen 6 desktop processors, the market should be ready with memory modules that will mean even the highest core count Zen 6 parts will be at worst only slightly more bandwidth-starved than their predecessors. And the lower core count Zen 6 CPUs with a single CCD should be able to provide substantially more bandwidth than their predecessors. All without requiring DDR6 yet.
That must be the reason, why EPYC 9175F exists. It is only 16-core CPU, but all 16 8-core CCDs are populated and only one core on each is active.
The next gen EPYC is rumored to have 16 instead of 12 memory channels (which were 8 only 4-5 years ago).
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